High resolution rail-to-rail ADC in CMOS digital technology
نویسندگان
چکیده
This paper discusses the design issues for an high resolution rail-to-rail analog-to-digital converter. The circuit proposed uses conventional digital technology (without precise capacitors) and allows 12 bits of resolution to be achieved using 2.4 V bias and 2.4 V input dynamic range. The proposed architecture is based on the successive algorithm technique and uses a rail-to-rail autozeroed comparator. A method to digitally correct errors from the first part of the conversion cycle is also discussed.
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